Semiconductor processing methods of forming a contact opening to a conductive line and methods of forming substrate active area source/drain regions

ABSTRACT

In one aspect, the invention provides a method of forming a contact opening to a conductive line. In one preferred implementation, a contact opening is formed to a conductive line which overlies a substrate isolation area with an etch which also outwardly exposes substrate active area to accommodate source/drain doping. In another preferred implementation, desired PMOS regions over a substrate into which p-type impurity is to be provided are exposed while a contact opening is contemporaneously formed to at least one conductive line extending over substrate isolation oxide. In another preferred implementation, a contact opening to a conductive line over a substrate and an opening to a laterally spaced substrate active area are formed in a common masking step. In another preferred implementation, desired PMOS active areas over a substrate are exposed and p-type impurity to a first concentration is provided into desired exposed areas. A masking layer is formed over the substrate and subsequently patterned and etched to form openings over source/drain regions. P-type impurity is provided through the openings into the source/drain regions to a second concentration which is greater than the first concentration.

TECHNICAL FIELD

[0001] This invention relates to semiconductor processing methods offorming integrated circuitry and in particular, to methods of formingcomplementary metal oxide semiconductor (CMOS) circuitry. The inventionalso relates to semiconductor processing methods of forming a contactopening to a conductive line.

BACKGROUND OF THE INVENTION

[0002] High density integrated circuitry is principally fabricated fromsemiconductor wafers. An MOS (metal-oxide-semiconductor) structure insemiconductor processing is created by superimposing several layers ofconducting, insulating and transistor forming materials. After a seriesof processing steps, a typical structure might comprise levels ofdiffusion, polysilicon and metal that are separated by insulatinglayers. Upon fabrication completion, a wafer contains a plurality ofidentical discrete die areas which are ultimately cut from the wafer toform individual chips. Die areas or cut dies are tested for operability,with good dies being assembled into separate encapsulating packageswhich are used in end-products or systems.

[0003] CMOS is so-named because it uses two types of transistors, namelyan n-type transistor (NMOS) and a p-type transistor (PMOS). These arefabricated in a semiconductor substrate, typically silicon, by usingeither negatively doped silicon that is rich in electrons or positivelydoped silicon that is rich in holes. Different dopant ions are utilizedfor doping the desired substrate regions with the desired concentrationof produced holes or electrons.

[0004] NMOS remained the dominant MOS technology as long as theintegration level devices on a chip was sufficiently low. It iscomparatively inexpensive to fabricate, very functionally dense, andfaster than PMOS. With the dawning of large scale integration, however,power consumption in NMOS circuits began to exceed tolerable limits.CMOS represented a lower-power technology capable of exploiting largescale integration fabrication techniques.

[0005] Fabrication of semiconductor circuitry includes numerousprocessing steps in which certain areas of a semiconductor substrate aremasked while other areas are subjected to processing conditions such asvarious etching steps and doping steps. In an effort to optimizesemiconductor processing, efforts in the industry have been focused onreducing the number of processing steps in any particular processingflow. Reducing the number of processing steps required in a particularprocessing flow saves valuable processing time and subjects the wafer toless risk of destruction.

[0006] In typical CMOS processing, separate photomasking processingsteps are utilized to both open up contact openings to conductive linesformed over the substrate, as well as to expose substrate active areasinto which dopants or conductivity changing impurity were to be added.Such separate processing of course adds to processing time and effort.It is desirable to reduce the number of required processing stepsassociated with forming integrated circuitry. It is also desirable toimprove upon current semiconductor processing techniques.

[0007] This invention arose out of concerns associated with reducing thenumber of processing steps required to produce integrated circuitry inparticular CMOS circuitry. This invention also grew out of concernsassociated with improving formation of PMOS active area diffusionregions associated with CMOS circuitry.

SUMMARY OF THE INVENTION

[0008] In one aspect, the invention provides a method of forming acontact opening to a conductive line. In one preferred implementation,an etch is conducted to form a contact opening to a conductive linewhich overlies a substrate isolation area. The same etch also,preferably, outwardly exposes substrate active area to accommodatesource/drain doping. In another preferred implementation, desired PMOSregions over a substrate into which p-type impurity is to be providedare exposed while a contact opening is contemporaneously formed to atleast one conductive line extending over substrate isolation oxide. Inanother preferred implementation, a contact opening to a conductive lineover a substrate and an opening to a laterally spaced substrate activearea are formed in a common masking step.

[0009] In another preferred implementation, desired PMOS active areasover a substrate are exposed and p-type impurity to a firstconcentration is provided into desired exposed areas. Such preferablydefines at least a portion of source/drain regions to be formed. Amasking layer is formed over the substrate and subsequently patternedand etched to form openings over desired source/drain regions. P-typeimpurity is then provided through the openings and into the source/drainregions to a second concentration which is greater than the firstconcentration.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0011]FIG. 1 is a cross-sectional view of a semiconductor wafer fragmentat one processing step in accordance with the invention.

[0012]FIG. 2 is a cross-sectional view of the FIG. 1 semiconductor waferfragment at a processing step subsequent to that shown by FIG. 1.

[0013]FIG. 3 is a cross-sectional view of the FIG. 1 semiconductor waferfragment at a processing step subsequent to that shown by FIG. 2.

[0014]FIG. 4 is a cross-sectional view of the FIG. 1 semiconductor waferfragment at a processing step subsequent to that shown by FIG. 3.

[0015]FIG. 5 is a cross-sectional view of the FIG. 1 semiconductor waferfragment at a processing step subsequent to that shown by FIG. 4.

[0016]FIG. 6 is a cross-sectional view of the FIG. 1 semiconductor waferfragment at a processing step subsequent to that shown by FIG. 5.

[0017]FIG. 7 is a cross-sectional view of an alternate conductive lineconstruction made in accordance with the invention.

[0018]FIG. 8 is a cross-sectional view of the FIG. 1 semiconductor waferfragment at an alternate processing step subsequent to that shown inFIG. 3.

[0019]FIG. 9 is a cross-sectional view of the FIG. 8 semiconductor waferfragment at a processing step subsequent to that shown by FIG. 8.

[0020]FIG. 10 is a cross-sectional view of the FIG. 8 semiconductorwafer fragment at a processing step subsequent to that shown by FIG. 9.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0022] Referring to FIG. 1, a semiconductive substrate in process isindicated generally with reference numeral 10. Preferably, such iscomprised of a bulk monocrystalline silicon substrate 11 having variouslayers deposited or otherwise formed thereover. In the context of thisdocument, the term “semiconductive substrate” is defined to mean anyconstruction comprising semiconductive material, including, but notlimited to, bulk semiconductive materials such as a semiconductive wafer(either alone or in assemblies comprising other materials thereon), andsemiconductive material layers (either alone or in assemblies comprisingother materials). The term “substrate” refers to any supportingstructure, including, but not limited to, the semiconductive substratesdescribed above.

[0023] Semiconductive substrate 10, in the illustrated and preferredembodiments is undergoing processing in which CMOS circuitry is formed.Accordingly, an n-well 12 is provided within substrate 11 for supportingthe formation of PMOS circuitry and comprises PMOS active area region 14within PMOS region 15. Corresponding NMOS circuitry is depicted byreference numeral 16 and comprises a conductive line 24 in theillustrated cross section. Line 24 is operatively connected tocorresponding NMOS active area regions which are not specifically shown.

[0024] Typically, active area regions such as PMOS active area region 14include at least one conductive line 22 which extends thereover andprovides a gate line stack for MOS transistors to be subsequentlyformed. According to one aspect of the invention, lines 22 and 24comprise conductive gate or word lines which overlie one or more fieldisolation regions, areas or field oxide regions such as regions or areas26 which extend into and out of the page. Other conductive lines, andones which do not necessarily extend over the to-be-described PMOS andNMOS active areas can undergo processing in accordance with theinvention, as will become apparent below.

[0025] In accordance with one preferred methodical aspect of theinvention, desired PMOS active area regions 14 are exposed oversemiconductive substrate 10 while a contact opening to at least oneconductive line is formed: Preferably, the PMOS region is exposed andthe contact opening is formed using a common masking step. This isadvantageous because at least one masking step can be eliminated in theprocess flow.

[0026] Conductive line 22 includes a gate oxide layer 28 atop which apolysilicon layer 30, a silicide layer 32 and a protective nitridecontaining cap or capping layer 34 are formed. Sidewall spacers 36 arepreferably formed from a suitable nitride material and overlie sidewallsof the gate line. Together, nitride cap 34 and sidewall spacers 36 forma protective nitride encapsulation layer over conductive gate line 22.Conductive line 24 is preferably formed contemporaneously withconductive line 22. Accordingly, it as well comprises gate oxide layer28, polysilicon layer 30, silicide layer 32, protective nitridecontaining cap or capping layer 34 and protective sidewall spacers 36.As with conductive line 22, nitride containing cap or capping layer 34together with sidewall spacers 36 form a protective nitrideencapsulation layer over conductive line 24. For purposes of ongoingdiscussion, conductive lines 22, 24 comprise a plurality of layers whichwere previously formed over semiconductive substrate 10, andsubsequently etched to form or produce the conductive lines. Theillustrated and preferred conductive lines have respective conductiveline tops 35 over which the protective nitride material 34 is formed.

[0027] Referring still to FIG. 1, a thin layer of oxide 38 is formedpreferably through decomposition of tetraethylorthosilicate (TEOS). Anoxide layer 40, preferably borophosphosilicate glass (BPSG), is formedthereover.

[0028] Referring to FIG. 2, layer 40 is planarized, as by suitablemechanical abrasion of semiconductive substrate 10. An examplemechanical abrasion process is chemical-mechanical planarization. Otherplanarization techniques are of course possible.

[0029] Referring to FIGS. 3 and 4, a layer of photoresist 42 is formedover semiconductive substrate 10 (FIG. 3) and subsequently patterned(FIG. 4) to form or define a doping window 44 over PMOS active region14, and a contact opening 46 over conductive line 24. In the illustratedand preferred embodiment, doping window 44 has a first open lateralwidth dimension W₁ and contact opening 46 has a second open lateralwidth dimension W₂. Second open lateral width dimension W₂ is less thanthe first open lateral width dimension W₁.

[0030] Referring to FIG. 5, and in the illustrated common masking step,oxide layers 40 and 38 are etched downwardly to outwardly expose PMOSactive area region 14, and more specifically, to expose PMOS activeareas into which p-type impurity is to be provided. In the same step,contact opening 46 is formed or etched over conductive line 24 overlyingthe field isolation region 26. As shown, the etch forming contactopening 46 will typically remove at least some of the nitride materialforming nitride cap 34 and hence outwardly expose a portion of silicidelayer 32 thereunder. Accordingly, the etch also removes the nitride capover conductive gate line 22 and etches spacers 36 downwardly as shown.At this point, enough of the oxide layer over the substrate active areahas typically been removed to outwardly expose desired source/drainregions and accommodate doping of the source/drain regions with p-typeimpurity adjacent gate line 24.

[0031] According to one aspect of the invention, the contact opening isformed and the substrate active area is exposed utilizing oneanisotropic etch which preferably etches oxide material and nitridematerial at substantially the same rate. Alternately, two separateetches can be used to expose the substrate active area. An exemplaryetch can be a first anisotropic dry etch followed by a wet etch. Otheretching regimes are of course possible.

[0032] Referring still to FIG. 5, and at a processing point where theillustrated patterned photoresist is still in place over the substrate,p-type impurity is provided into the substrate to form diffusion regions48. As provided, diffusion regions 48 define at least portions ofdesired doped source/drain regions. Suitable p-type dopants includeboron, BF₂, and the like. Such doping of regions 48 can be carried out,for example, by ion implantation. One preferred method is angled iondoping at some significant angle from vertical (i.e. between about 0°and 45°), with substrate 10 being rotated during such doping. Otherangles are possible. Such angled ion doping results in little, if any,dopant reaching the exposed portion of conductive line 24. This isbecause the lateral width of doping window 44 provides a much largertarget area than the relatively narrow lateral width of the contactopening 46 over conductive line 24.

[0033] Alternately and more preferred, the patterned photoresist 42 isstripped as shown in FIG. 6 prior to forming diffusion regions 48. Apreferred doping technique in such instance is gas chemical diffusion.One advantage of gas chemical diffusion over the above described ionimplantation is the formation of shallower junctions having heaviersurface doping. Shallower junctions are advantageous because lesslateral diffusion occurs during downstream heat processing of thesubstrate. Heavier surface doping is advantageous because such desirablyreduces contact resistance when contacts are subsequently formed or madeto such regions. Accordingly, such provides an example of forming PMOSsource/drain regions over semiconductive substrate 10 in the absence ofany photoresist over NMOS regions of the substrate. Such can howeverresult in provision of PMOS dopant within a portion of the lateral widthof line 24 and particularly silicide layer 32. Any conductivity changeresulting from the introduction of dopant into silicide layer 32 is, toa desirable extent, mitigated by the narrower width of opening 46 ascompared to the lateral width of line 24 itself. Accordingly, circuitoperability is maintained.

[0034] Alternately, processing the substrate in accordance with theabove-described approach could also be used to effect formation of NMOSsource/drain regions over a substrate in the absence of any photoresistover PMOS regions of the substrate.

[0035] Referring to FIG. 7, an alternate conductive line and/or gatestack 50 is shown. Such construction can be used to mitigate theabove-described etch into silicide layer 32 of conductive line 24 (FIGS.5 and 6) when the doping window and contact opening 46 are formed. Inthe figure, like elements have been similarly designated. Accordingly,line 50 comprises a conductive portion atop a gate oxide layer 28. Theconductive portion comprises polysilicon layer 30 and silicide layer 32thereatop. Line 50 also includes a protective portion or capping layer51 formed over the conductive portion. According to a preferred aspectof the invention, the protective portion includes a nitride layer 52deposited to a thickness of around 300 Angstroms, and an oxide layer 54elevationally outwardly of and atop the nitride layer. Layer 54 can beprovided by suitable decomposition of TEOS, with an example thicknessfor layer 54 being around 200 to 600 Angstroms. A nitride encapsulationmaterial 56 is subsequently provided or formed over the conductive line.Hence when contact opening 46 is formed as described above, at leastsome of the nitride encapsulation material 56 and some of the protectiveportion, including upper oxide portion 54 are removed. Preferably, suchremoved portions leave behind enough of nitride layer 52 to provide aprotective cap or cover over the conductive line. One manner of formingcontact opening 46 which capitalizes on such alternate conductive lineis to first etch or otherwise remove a portion of nitride encapsulationmaterial 56 substantially selective to oxide portion 54, and then toremove at least a portion of oxide portion 54 substantially selective tonitride layer 52. Such leaves at least some of nitride layer 52 oversilicide layer 32 which desirably shields the underlying conductiveportion of line 50 during the p-type doping described above.

[0036] The above described methodology enables contemporaneous formationof a contact opening to at least one conductive line and exposure ofdesired substrate active regions or areas into which dopants orimpurities are to be provided. According to a preferred aspect of theinvention, the desired substrate active areas comprise PMOS active areaswhich form part of a CMOS integrated circuit. According to anotherpreferred aspect of the invention, the contact opening is formed to aconductive line which includes a portion which extends over substrateactive area and which provides a conductive gate or word line thereto.In one implementation, such conductive line overlies a field isolationregion and extends laterally away therefrom and over a substrate activearea. Such process represents an improvement over previous processes inat least the following ways. First, a masking step can be eliminated.Second, a heavier p-type doping step is conducted much later in theprocessing flow which minimizes undesired thermally-effected diffusionof p+ regions, as such are not subjected to as much thermal processingas if such were formed earlier in the process. Third, gas phase dopingcan take place to form desired substrate diffusion regions instead ofthe above-described ion implantation.

[0037] Referring to FIGS. 8-10, a process methodology is described whichis advantageous in that such lowers contact resistance for subsequentlyformed contacts to p+ diffusion regions. Like numbers from the firstdescribed embodiment are utilized where appropriate, with differencesbeing indicated with the suffix “a” or with different numerals. Suchprocess provides a better “off” state for PMOS transistors by minimizinglateral spread of the high concentration of the p+ material in PMOSsource/drains. Such greatly reduces the risk of current leakage beneaththe gates in channel regions.

[0038] Semiconductive substrate 10 a is shown in FIG. 8 at a processingstep before layers 38 and 40 are deposited in FIG. 3. A photoresistlayer 42 a is formed over substrate 10 a.

[0039] Referring to FIG. 9, photoresist layer 42 a is suitably patternedto define a doping window 44 a over PMOS active area 14 and not theabove described contact opening 46 (FIG. 4). P-type impurity is providedinto exposed substrate source/drain active area regions to a firstconcentration. A suitable concentration of p-type impurity is betweenabout 1×10¹⁸ cm⁻³ and 1×10²⁰ cm⁻³. Such defines p-type diffusion firstregions 58. Thereafter, photoresist layer 42 a is removed and layers 38a and 40 a can be deposited and planarized as in FIG. 3.

[0040] Referring to FIG. 10, a masking layer 60 is formed over thesubstrate and subsequently layers 40 a and 38 a are patterned and etchedto form openings 62, 64 over diffusion first regions 58. Such etch mayadvantageously be the same etch which opens up contact opening 46 (FIG.4) to conductive line 24. Openings 62, 64 are smaller in cross-sectionthan the diffusion regions over which such are formed. P-type impurityis then provided through openings 62, 64 to a second concentration whichis greater than the first concentration. An exemplary concentration ofp-type impurity is between 1×10²⁰cm ⁻³ and 5×10²⁰cm ⁻³. Such formsp-type diffusion second regions 66 which constitute at least a portionof the source/drain regions. The remainder of the processing to form thedesired circuitry can take place in accordance with practices understoodand appreciated by those of skill in the art.

[0041] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A semiconductor CMOS processing method of forming NMOS and PMOScircuitry comprising exposing desired PMOS regions over a substrate intowhich p-type impurity is to be provided while contemporaneously forminga contact opening to at least one conductive line extending overisolation oxide.
 2. The CMOS processing method of claim 1 furthercomprising prior to the exposing forming at least one nitride containinginsulative cap over the at least one conductive line.
 3. The CMOSprocessing method of claim 1 further comprising prior to the exposingforming an insulative cap over the at least one conductive line, theinsulating cap comprising a nitride layer and an oxide layer thereatop.4. The CMOS processing method of claim 1 further comprising: prior tothe exposing, forming an insulative cap over the at least one conductiveline, the insulating cap comprising a nitride layer and an oxide layerthereatop, the step of forming the contact opening leaving behind atleast some of the nitride layer; and after the exposing, providingp-type impurity into the exposed PMOS regions to form desiredsource/drain regions.
 5. The CMOS processing method of claim 1, whereinthe exposing and the forming are accomplished using at least two etches.6. The CMOS processing method of claim 1, wherein the exposing andforming are accomplished using a wet etch and a dry etch.
 7. The CMOSprocessing method of claim 1, wherein the exposing and forming areaccomplished using at least two etches, a first of which comprises a dryetch.
 8. A semiconductor processing method comprising in a commonmasking step, forming a contact opening to a conductive line over asubstrate and forming an opening to a laterally spaced substrate activearea.
 9. The CMOS processing method of claim 8, wherein the conductiveline includes a nitride containing cap a portion of which is removedduring formation of the contact opening.
 10. The CMOS processing methodof claim 8 further comprising: prior to the forming steps, forming aphotoresist layer over the substrate and patterning the photoresistlayer with a desired contact opening and an opening to a laterallyspaced substrate active area, wherein the steps of forming a contactopening and an opening to the laterally spaced substrate active areacomprise anisotropically etching a protective material over theconductive line to define the contact opening with a desired lateralwidth dimension, the etch also defining a doping window through whichimpurity is to be provided to the substrate active area, the dopingwindow having a lateral width dimension which is greater than thelateral width dimension of the contact opening; and after the etchingstep, angle doping :the substrate with a p-type impurity to form atleast one source/drain region in the active area.
 11. A semiconductorCMOS processing method of forming PMOS source/drain regions over asubstrate comprising doping desired PMOS source/drain regions in theabsence of any photoresist over NMOS regions of the substrate.
 12. TheCMOS processing method of claim 11 wherein the doping step is carriedout by ion implantation.
 13. The CMOS processing method of claim 11wherein the doping step is carried out by gas chemical diffusion. 14.The CMOS processing method of claim 11 further comprising prior to thedoping step: forming an oxide layer over the substrate; and in a commonmasking step, patterning: a) a contact opening to a conductive lineextending over isolation oxide and, b) a doping window to a substrateactive area which is to retain the PMOS source/drain regions.
 15. Asemiconductor CMOS processing method of forming NMOS source/drainregions over a substrate comprising doping desired NMOS source/drainregions in the absence of any photoresist over PMOS regions of thesubstrate.
 16. A semiconductor CMOS processing method comprising, in thesame processing steps, exposing PMOS active areas on a substrate intowhich p-type impurity is to be provided and forming contact openings tosubstrate gate lines.
 17. The CMOS processing method of claim 16,wherein the gate lines include a protective cap at least a portion ofwhich contains a nitride material and the forming step comprisesremoving at least some of the protective cap.
 18. The CMOS processingmethod of claim 16, wherein the gate lines include a protective cap atleast a portion of which contains a nitride material with an oxidematerial elevationally outward thereof, and the forming step comprisesremoving at least some of the protective cap.
 19. The CMOS processingmethod of claim 16 further comprising after the exposing and formingsteps, gas diffusion doping the exposed PMOS active areas to formsource/drain regions.
 20. A semiconductor processing method of forming acontact opening to a conductive gate line which overlies a substrateactive area and substrate isolation area comprising, in a common maskingstep, patterning and etching a contact opening to a portion of theconductive gate line which overlies the substrate isolation area, thepatterning and etching also outwardly exposing substrate active area toaccommodate source/drain doping adjacent the gate line in the substrateactive area.
 21. The semiconductor processing method of claim 20,wherein the conductive gate line includes a nitride containing cap aportion of which is removed during formation of the contact opening. 22.The semiconductor processing method of claim 20, wherein the conductiveline includes a nitride containing cap with an upper oxide portion whichis removed during formation of the contact opening to expose at leastsome of the nitride containing portion.
 23. The semiconductor processingmethod of claim 20, wherein the etching defines a doping window throughwhich the desired substrate active area is exposed, the doping windowhaving a greater lateral width dimension than the contact opening. 24.The semiconductor processing method of claim 20, wherein the etchingdefines a doping window through which the desired substrate active areais exposed, the doping window having a greater lateral width dimensionthan the contact opening and further comprising angle doping the exposedsubstrate active area to form source/drain regions.
 25. A semiconductorCMOS processing method comprising: forming a doping window over a PMOSactive area on a substrate, the doping window having a first openlateral width; forming a contact opening over a conductive line, thecontact opening having a second open lateral width which is less thanthe first open lateral width; and after forming the doping window andcontact opening, subjecting the substrate to angled ion implant dopingof p-type material to form PMOS source/drain regions in the PMOS activearea.
 26. The CMOS processing method of claim 25, wherein forming thedoping window and a contact opening are accomplished in a common maskingstep.
 27. The CMOS processing method of claim 25, wherein the conductiveline comprises a polysilicon layer, a silicide layer atop thepolysilicon layer, and a protective capping layer atop the silicidelayer, the protective capping layer comprising at least one nitridelayer and an oxide layer atop the at least one nitride layer.
 28. Asemiconductor processing method of forming PMOS circuitry having PMOSsource/drain regions over a semiconductor substrate comprising: exposingdesired PMOS source/drain active areas over the substrate; providingp-type impurity to a first concentration into the exposed PMOSsource/drain active areas; forming a masking layer over the substrate;patterning and etching the masking layer to form openings over the PMOSsource/drain active areas; and providing p-type impurity through theopenings into the PMOS source/drain active areas to a secondconcentration which is greater than the first concentration.
 29. Thesemiconductor processing method of claim 28 further comprising formingNMOS circuitry over the substrate, the PMOS circuitry and the NMOScircuitry collectively defining CMOS circuitry.
 30. The semiconductorprocessing method of claim 28, wherein the openings are smaller in crosssection than the source/drain regions.
 31. The semiconductor processingmethod of claim 28, wherein the patterning and etching comprises formingat least one contact opening to a conductive line formed over thesubstrate.
 32. A semiconductor processing method of forming a contactopening to a conductive word line which overlies a substrate active areacomprising: forming a conductive word line over a substrate, a portionof the word line overlying a field isolation region and extendinglaterally away therefrom and over a substrate active area; encapsulatingthe word line with nitride encapsulating material; forming an oxidelayer over the substrate, the oxide layer covering the conductive wordline and the substrate active area; and in a common step, patterning andetching the oxide layer to outwardly expose at least one desiredsubstrate active area into which p-type impurity is to be provided, theetching also forming a contact opening over that portion of theconductive word line overlying the field isolation region.
 33. Thesemiconductor processing method of claim 32, wherein the etching stepetches the oxide material at substantially the same rate as the nitrideencapsulating material.
 34. A semiconductor processing methodcomprising: forming at least one conductive gate line over a substrate,the gate line including a silicide layer, the gate line overlying afield isolation region and extending laterally away therefrom and oversubstrate active area; providing a nitride material over the silicidelayer; forming an oxide layer over the at least one conductive line andthe substrate active area; and conducting an anisotropic etch to adegree sufficient to: (a) remove at least some of the nitride materialover the conductive line to define a contact opening thereto and, (b)remove enough of the oxide layer over the substrate active area toexpose source/drain regions into which p-type impurity is to be added.35. The semiconductor processing method of claim 34, wherein the nitridematerial and the oxide layer are etched at substantially the same rate.36. The semiconductor processing method of claim 34 further comprisinggas diffusion doping the exposed source/drain regions with a p-typeimpurity.
 37. A semiconductor processing method of forming a contactopening to a conductive line comprising: forming a conductive line overa substrate, the conductive line having a conductive portion and aprotective portion over the conductive portion, the protective portioncomprising at least a nitride layer atop the conductive line and anoxide layer atop the nitride layer, at least a part of the conductiveline extending over a substrate active area; forming nitrideencapsulation material over the conductive line and its protectiveportion; and in a common masking step, etching a doping window openingover the substrate active area adjacent the line and removing at leastsome of the nitride encapsulation material and some of the protectiveportion of the conductive line to form a contact opening to theconductive line.
 38. A semiconductor method of forming a conductive linecomprising: forming a conductive gate stack atop a substrate; forming anitride layer atop the gate stack; forming an oxide layer atop thenitride layer; forming nitride encapsulation material over the oxidelayer, the nitride layer and the conductive gate stack; selectivelyremoving at least some of the nitride encapsulation material relative tothe oxide layer; and selectively removing at least some of the oxidelayer relative to the nitride layer, the removing steps defining atleast part of a contact opening over the gate stack.
 39. A semiconductorCMOS processing method of forming CMOS circuitry comprising: forming asubstrate comprising a plurality of layers; etching at least some of theplurality of layers to form at least one conductive gate line, the atleast one gate line overlying a field isolation region and having aconductive line top; forming a nitride material over at least a portionof the conductive gate line top; forming an oxide layer over the nitridematerial; planarizing the oxide layer; forming a photoresist layer overthe planarized oxide layer; in a common masking step, patterning thephotoresist layer to form a contact opening over the conductive gateline and a doping window over active area of the substrate adjacent thegate line, the contact opening and the doping window having respectivelateral width dimensions, the contact opening width dimension being lessthan the doping window width dimension; anisotropically etching both thenitride material and the oxide layer at substantially the same rate torespectively define a contact opening to the conductive gate line and adoping window over the substrate active area adjacent the gate line; anddoping desired areas of the substrate active area with a p-type impurityto form at least a portion of *one source/drain region.